1. Did IRAM ever end up in anything remotely commercially-successful?
2. Is there any movement to eliminate or simplify memory controllers by throwing more RAM chiplets in manycore CPUs? The gradient vector in SOCs points to including a fixed amount of RAM anyhow.
Rendered at 17:52:31 GMT+0000 (Coordinated Universal Time) with Vercel.
1. Did IRAM ever end up in anything remotely commercially-successful?
2. Is there any movement to eliminate or simplify memory controllers by throwing more RAM chiplets in manycore CPUs? The gradient vector in SOCs points to including a fixed amount of RAM anyhow.